The present invention relates generally ion-implanted junction field effect transistors (I.sup.2 JFET) and more specifically for an improved method of fabricating ion-implanted JFETs with self-aligned sources and drains as well as self-aligned gates for improved radiation tolerances.
The JFETs may be of single conductivity type or complementary. The present technology for adding ion-implanted JFETs (I.sup.2 JFETs) to a bipolar process requires that the JFET drain and source be formed with the base or emitter diffusion of the bipolar transistor with the channel and top gate being ion implanted therebetween. A typical example is U.S. Pat. No. 4,495,694 to Beasom and 4,596,068 to Peters. Both of these diffusions are optimized toward obtaining the best performance from the bipolar transistors. The performance (i.e. speed) of the I.sup.2 JFETs is limited by the gate-source capacitance. This capacitance is substantial when the drain and source are formed with the transistor base or emitter diffusion. Since I.sup.2 JFETs are formed with implanted channel depths of about 0.1-0.2 um and typical emitter diffusions are 1-2 um deep, the drain and source formed from emitter or base diffusions extend far below the JFET channel. This adds to the drain and source to gate capacitance. Gate to source capacitance directly limits the speed of the JFET.
A further limitation of the present I.sup.2 JFET/bipolar transistor technology arises from the necessity to align the I.sup.2 JFET thin oxide to the emitter or base diffusion. The overlap of the thin oxide to emitter or base diffusion limits how small one can reduce the drain and source width. The requirement to maintain a drain and source stripe wide enough to allow for misalignment of thin oxide to the drain and source adds to the capacitance of the drain and source to gate.
Another disadvantage of the present technology which uses the emitter or base diffusion of the bipolar transistors to form the drain and source of the I.sup.2 JFET is the necessity to make the drain and source stripes wide enough to prevent the contact aperture oxide cut from crossing the drain/source to bottom gate junction. If this misalignment were to occur, the subsequent metal interconnect deposition would short the drain/source to bottom gate as shown in the cross-section of FIG. 1. The requirement to make the drain and source stripes wide enough to prevent the misalignment of contact apertures to drain and source (i.e. base or emitter) adds to the drain and source to gate capacitance of the device.
Present application of ion-implanted JFETs (I.sup.2 JFETs) in radiation hardened linear circuits requires nominal V.sub.pinchoff of 1.0-1.5 V, and BV.sub.DSS of 20-40 V. Resistance to neutron and total dose gamma radiation requires thin channels and high carrier concentrations in the channel and top gate. In the present I.sup.2 JFET technology, BV.sub.DSS is limited by the top gate/drain-source junction gradient as discussed in U.S. Pat. No. 4,683,485. Increasing top gate concentration and channel concentration to improve neutron and total dose gamma hardness sacrifices BV.sub.DSS. The large junction area of the drain-source/bottom gate junction in the current technology I.sup.2 JFETs contributes to excessive post-radiation leakage currents.
It is an object of the present invention to improve the speed and reduce the size of I.sup.2 JFETs by eliminating the emitter or base diffusion of the source drain.
Another object of the present invention is to form the source and drain so as to just contact the implanted channel for minimizing the drain and source capacitance to the gate.
Still a further object of the present invention is to provide a method of forming I.sup.2 JFETs wherein the source and drains are formed concurrent with the activation of the ion implanted top gate and channel to optimize the process control and simplicity.
An even further object of the present invention is to provide a method of fabricating I.sup.2 JFETs wherein the source and drains are self aligned to the contact thereby improving speed and reducing size.
Still a further object of the present invention is to provide a radiation hard linear device without sacrificing the source to drain breakdown voltage.
An even further object of the present invention is to provide a method of fabricating complementary I.sup.2 JFETs which are radiation tolerant or hardened devices.
These and other objects of the invention are obtained by the following techniques. The improvement in speed and reduction in size of the I.sup.2 JFETs results from eliminating the use of emitter or base diffusions for forming the source and drain regions. The source and drain regions according to the present invention are formed by out-diffusion from a contact material, for example deposited polycrystalline silicon which includes the appropriate doping impurities. The structure is heated to diffuse the impurities from the contact material into the substrate to form self-aligned source and drains and source and drain contacts. The self-alignment feature of the contacts to the source and drain permits the source and drain stripe width to be reduced to that of a single oxide cut width. This area reduction decreases drain and source to gate capacitance and shrinks the device size drastically. Thus the JFET's speed and device packing density are both improved.
The out-diffusion to form the source and drain can be performed at the same time as the activation of the ion-implanted top gate and channel implants so as to optimize process control and simplicity. The out-diffusion of the impurities from the contacts are limited such as to just engage the channel, thereby minimizing the source and drain capacitance to gate. For the simplicity of method, the ion implantation for the top gate and channel are performed prior to heating. The ion implantation of the top gate and channel may take place before or after depositing of the contact material. As an alternative, the contact material may be deposited and heated for out-diffusion before the ion implantation for the top gate and channel. This will require a second heating step to activate the ion implanted top gate and channel impurities.
As a further alternative, the ion-implantation for the channel region may be performed first followed by the formation of the source and drain contact material. The top gate is then formed using the source and drain contact material as the alignment mask. Upon heat treating to activate the ion imPlanted impurities and out-diffuse the source and drains from the source and drain contact material, the ultimately formed source and drain are spaced laterally from the top gate. This produces self-aligned top gate in addition to the self-aligned source and drains. The resulting source and drain regions are made with shallower junctions than the prior art and thereby reduce the junction area. This decreases the radiation induced leakage current. The separation of the source and drain heavily doped regions from the top gate region permits increased channel and top gate concentration for better radiation tolerance without sacrificing BV.sub.DSS.
As an alternative to the out-diffusion of the source and drain material from the source and drain contact, the self-aligned gate technique may also be used by ion-implanting the source and drain regions. This is followed by forming the source and drain contact material and using it as a mask to perform the ion implantation of the self-aligned gate which will be spaced from the source and drain contact regions upon activation of the ion-implanted impurities.
To further increase the radiation hardness of the device in the self-aligned gate technique, a dual channel implant may be performed. Channel impurities are introduced to a first depth of first impurities concentration to form the active channel region. A second ion-implantation of channel impurities at a second depth and second impurity concentration less than the first depth and first concentration is performed to enhance the channel region at the surface space between the source and drain top gate regions. This allows for maximum active channel doping for neutron hardness and independent control of the channel surface doping for optimum balance of total dose gamma hardening versus BV.sub.DSS. The ion implantation to form an enhanced channel region is conducted through a thin oxide layer so as to have a peak concentration at the interface of the substrate and this thin oxide layer.
The above techniques may be used in a process to form complementary junction field effect transistors with appropriate masking provided to sequentially form corresponding portions of the complementary JFETs. Preferably the process includes the self-aligned gate technique with the double implanted channel region for each of the complementary JFETs. The complementary process using the self-aligned source and drains as being out-diffused from the contact material would include the additional steps of laying the contact material as a single layer and providing an appropriate mask for the two separate doping steps of the contact material. This reduces the requirements of two different deposition steps for the contact material to be used as an out-diffusion source for the individual sources and drains for the two types of conductory type JFETs.